The present invention relates to a large scale integrated circuit (LSI) semiconductor device, more precisely, to a very large scale integrated (VLSI) circuit semiconductor device where the entire area of a semiconductor wafer or slice is used for fabricating the circuit thereof. It is especially involved with a device that can replace the wafer or the slice containing some defects in order to increase the production yield of the device.
Recently, LSI circuits are increasing its integration scale, and increasing its chip size. Along with this tendency, a VLSI circuit is made using the entire area of the wafer or slice (hereinafter it will be referred to simply as a wafer), called a wafer integration circuit or a wafer IC. The most serious problem in making the circuit is fabricating yield, because any defect in the wafer will not allow the device to be completed.
Many attempts to overcome above difficulties and realize the wafer IC have been tried by semiconductor manufacturers. For example, among a number of chips formed in a wafer, only good ones are selected, being interconnected to each other to form a VLSI, without separating the chips from the wafer. Using this method, the problem of defects on the wafer can be avoided. The method is preferable for a VLSI which includes plurality of the same circuitries, such as a memory device. However, the number of and the kind of the chips included in the wafer are limited, because every type of circuits in the wafer must have redundant chips of each type. Accordingly, it cannot be considered to be a real wafer IC.
Another attempt is to replace a bad chip or bad portion with a good one. One approach is to pile a good chip 8, namely a repair chip, on the bad chip or bad portion in the wafer 1, as shown in FIG. 1, and connect bonding pads 9 on the repair chip 8 to bonding pads 4 on the wafer 1 using bonding wires 12. Another approach is, as shown in FIG. 2, to bond a repair chip 8 which has bonding bumps 9B to bumps 4B formed on the bad portion in a face-down bonding.
In all of the above attempts, since the good chips selected in the wafer are distributed on the wafer 1 in a random manner, the bondings between the chips differs from wafer to wafer and from defect point to defect point. Accordingly, the spare chips for replacing the bad chips or bad portion therewith must be prepared for all the anticipated defects in the wafer. This is quite undesirable with mass production. Moreover, additional technology must be developed to cut off the bad chip or the bad portion electrically from the wafer and bond a new chip on the same position. Therefore, at the present moment, it is still not practical to fabricate the wafer IC device in large quantity by the state-of-the-art technology.